While working at Fulcrum Acoustic I had some free time in the evenings. Rather than watching Netflix I figured that I’d start a project that had been on the back-burner for years.
The basic concept started as a credit card sized USB DAC and headphone amplifier to be given away in place of a business card. Over the course of the project it became clear that while the form factor would remain the BOM cost necessitated a different distribution strategy. The latest revision of the project costs about $60 per card in parts alone.
It is of note that at the time of this writing [6/17] the project is not yet finished and at least one more spin of the board will be necessary to produce a working headphone DAC.
There exist a multitude of chips on the market that promise USB input and audio output. In retrospect, for a first audio IO project I should have simply used one of these. The problem with virtually all of these products is that their specs are pretty bad. Most offer “CD quality” sound at 44.1 KHz sample rate and 16 bit depth. Don’t get me wrong, these specs are perfectly fine for most applications and I doubt that I, or any of my friends for that matter, would be able to appreciate a better converter, that said I wanted my device to be more versatile than these off the shelf solutions would allow.
With the all in one options ruled out I was left with the challenge of actually designing a more complex system. First I needed to find a solution to take a USB audio stream and convert it into a format that commonly available DAC chips can use. This standard is known as I2S. It is a two (audio) channel serial protocol that is flexible in what sample rates and bit depths it supports. I found my solution in the form of the XMOS XHRA-2HPA, a stereo USB 2.0 class complaint audio to I2S converter chip. Notably this chip is capable of 384 KHz 32 bit operation. Unfortunately this is not an inexpensive chip at around $13 BOM cost.
Once I picked the USB converter it was time to choose a DAC to work with it. Originally I planed to use a Cirrus logic converter but as I read through the data sheets for both the converter and the XMOS part I found no info as to weather the converter would work with a 32 bit zero padded stream. While it is possible that this converter would have worked I instead opted for a top of the line TI part which was capable of full 32 bit operation (in addition to 24 bit) at high sample rates.
Supporting circuitry was largely copied from the reference designs given by TI and XMOS with some modifications to make everything play well together.
I ran into a number of issues in the first spin of the PCBs. Most obviously I had chosen the wrong footprint for two of the components. One, and inductor, was an easy fix (22 vs 2.2 uH). The other, a switching regulator, had its footprint get mixed up with another part in my electrical cad and required green wire fixes on a part smaller than a grain of rice. Both of these issues would have been quickly caught had I been more careful in my review of the cad drawings before laying out the board.
The major issue that ensured that none of the first run of boards would be usable wouldn’t have been caught even in a through inspection of the cad files. My design uses a three channel clock generator chip from Silicon Labs to generate all of the clock signals needed for the converters operation. This clock generator takes I2C in to program its clock outputs. It turns out that all three outputs are not in fact independent. Two of the outputs share some internal circuitry and can not be changed without shutting down the other. While reading through the part’s data sheet I must have missed this as I ended up using one of those outputs as the main clock for the XMOS chip which was the device being used to send I2C information to the clock generator chip. Unfortunately this means that any time the output frequency of the clock generator chip is changed the XMOS core looses its system clock and stops functioning. A new board with fixed routing will take care of this issue.
Sam Feine 